ST20TP2BX50S Datasheet PDF

APPLICATIONS

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FEATURES

s Enhanced 32-bit VL-RISC CPU 0 to 50 MHz processor clock fast integer/bit operations very high code density s 8 Kbytes on-chip SRAM 200 Mbytes/s maximum bandwidth s Programmable memory interface 4 separately configurable regions 8/16/32-bits wide support for mixed memory 2 cycle external access support for page mode DRAM support for MPEG decoders support for PCMCIA CA module s Serial communications OS-Link 2 Programmable UARTs (ASC) 2 Synchronous serial interfaces (I2C) s Vectored interrupt subsystem Prioritized interrupts 8 levels of preemption 500 ns response time s DMA engines/interfaces 2 MPEG decoder DMAs 2 SmartCard interfaces Link IC DMA interface Section filter engine DVB descrambler DMA Block move DMA Teletext interface (I/O) IEEE 1284/ Transport out DMA s PWM/counter module Two 8-bit PWM Two 32-bit counters and capture registers s Low power controller Real time clock Watchdog timer s Programmable IO module s Professional toolset support ANSI C compile...