ST22FJ1M Datasheet | STMicroelectronics

FEATURES I 32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING I 768 KBYTES USER FLASH I 16 KBYTES USER RAM I 16 KBYTES USER SECONDARY RAM I 256 KBYTES USER PAGE-FLASH 32-BIT RISC CPU I DUAL INSTRUCTION SET, JAVACARD™ AND NATIVE I 4-STAGE PIPELINE I 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 11 SPECIAL REGISTERS I 4 MASKABLE INTERRUPT LEVELS I SUPERVISOR AND USER MODES SECURITY I CPU SECURITY INSTRUCTIONS - DES and 3DES instructions - Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography I CPU DPA/SPA COUNTERMEASURES I RANDOM NUMBER GENERATOR I HARDWARE RAM DESTRUCTION I CLOCK AND POWER MANAGEMENT I VOLTAGE AND CLOCK FREQUENCY SENSORS I ADVANCED MEMORY PROTECTION - Memory Protection Unit for application firewalling and peripheral access control - Domain switching securely controlled by protected Context Stack - Native/Java, Code/Data memory attributes with 256-byte granularity for Page-Flash, and 8-Kbyte granularity for Flash and ROM - Each FLASH sector can be independently set as read-only I FOUR WORKING STACKS - Java stack with both 16 and 32-bit accesses - User and Supervisor mode stacks - Security Context stack Figure 1. Delivery Form 4 4 4 Micromodule CRYPTOGRAPHIC LIBRARY ASYMMETRICAL ALGORITHMS - Software Crypto libraries in separate ROM area for efficient algorithm coding using a set of advanced functions. RSA, signature/ verification - RSA key calculation including Prime number generation SHA-1 I SYMMETRICAL ALGORITHMS - DES, Triple DES, AES CRYPTOGRAPHY PERFORMANCE The following table provides the cryptographic performances of the ST22FJ1M based on ST Crypto Library. Table 1. Preliminary Cryptographic Performances Algorithm RSA 1024 bits RSA 2048 bits DES SHA-1 AES-128 Function Signature with CRT Signature without CRT 2) Verification (e=0x10001) Signature with CRT Signature without CRT Verification (e=0x10001) Triple Single 512-bit Block Encryption including subkey putation Time 1) 79.0 ms 242.0 ms 3.6 ms 485.0 ms...