FEATURES
I 32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING I 768 KBYTES USER FLASH I 16 KBYTES USER RAM I 16 KBYTES USER SECONDARY RAM I 256 KBYTES USER PAGE-FLASH 32-BIT RISC CPU I DUAL INSTRUCTION SET, JAVACARD™ AND NATIVE I 4-STAGE PIPELINE I 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 11 SPECIAL REGISTERS I 4 MASKABLE INTERRUPT LEVELS I SUPERVISOR AND USER MODES SECURITY I CPU SECURITY INSTRUCTIONS – DES and 3DES instructions – Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography I CPU DPA/SPA COUNTERMEASURES I RANDOM NUMBER GENERATOR I HARDWARE RAM DESTRUCTION I CLOCK AND POWER MANAGEMENT I VOLTAGE AND CLOCK FREQUENCY SENSORS I ADVANCED MEMORY PROTECTION – Memory Protection Unit for application firewalling and peripheral access control – Domain switching securely controlled by protected Context Stack – Native/Java, Code/Data memory attributes with 256-byte granularity for Page-Flash, and 8-Kbyte granularity for Flash and ROM – Each FLASH secto...
STMicroelectronics
