FEATURES
32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING I 368 KBYTES USER ROM I 16 KBYTES USER RAM I 256K KBYTES USER EEPROM 32-BIT RISC CPU I DUAL INSTRUCTION SET, JAVACARD™ AND NATIVE I 4-STAGE PIPELINE I 16 GENERAL PURPOSE 32-BIT REGISTERS, AND SPECIAL REGISTERS I 4 MASKABLE INTERRUPT LEVELS I SUPERVISOR AND USER MODES SECURITY I CPU SECURITY INSTRUCTIONS – DES and 3DES instructions – Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography – CRC instruction I RANDOM NUMBER GENERATOR I EEPROM FLASH PROGRAMMING MODE I CLOCK AND POWER MANAGEMENT I VOLTAGE AND CLOCK FREQUENCY SENSORS I ADVANCED MEMORY PROTECTION – Memory Protection Unit for application firewalling and peripheral access control – Domain switching securely controlled by protected Context Stack – Native/Java, Code/Data memory attributes with 128-byte granularity I FOUR WORKING STACKS – Java stack with both 16 and 32-bit accesses – User and Supervisor mode stacks – Security Context stack I Figure 1.
STMicroelectronics
