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ST26C32AB - CMOS quad 3-state differential line receiver

General Description

The ST26C32AB is a quad differential line receiver designed to meet the RS-422, RS-423 standards for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.

Table 1.

Key Features

  • internal pull-up and pull-down resistors which prevent output oscillation on unused channels. The ST26C32AB provides an enable and disable function to all four receivers and features 3-state output with 6 mA source and sink capability. Features.
  • CMOS design for low power.
  • ± 0.2 V sensitivity over input common mode voltage range.
  • Typical propagation delay: 19 ns.
  • Typical input hysteresis: 60 mV.
  • Input will not load line when VCC = 0 V.
  • Meets.

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TSSOP16 ST26C32AB CMOS quad 3-state differential line receiver SO-16 Datasheet - production data The ST26C32AB has an input sensitivity of 200 mV over the common mode input voltage range of ± 7 V. The ST26C32AB features internal pull-up and pull-down resistors which prevent output oscillation on unused channels. The ST26C32AB provides an enable and disable function to all four receivers and features 3-state output with 6 mA source and sink capability. Features • CMOS design for low power • ± 0.