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ST33GxxxA
Secure MCU with 32-bit ARM® SecurCore® SC300™ CPU, SWP interface and high-density Flash memory, automotive grade
Data brief
DFN8 6 × 5 mm
Features
Hardware features ARM® SecurCore® SC300™ 32-bit RISC core
cadenced at 25 MHz 30 Kbytes of user RAM Up to 1280 Kbytes of user Flash memory with
OTP area Asynchronous receiver transmitter supporting
ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported) Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant) Serial peripheral interface (SPI) master/slave interface Three 16-bit timers with interrupt capability Seven general-purpose I/Os enabling proprietary protocol implementation 1.