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ST40RA - 32-bit Embedded SuperH Device

Key Features

  • s 32-bit SuperH CPU q q q q q Bus interfaces s Local memory interface SDRAM & DDR SDRAM q 64-bit hardware FPU (1.16 GFLOPS) 128-bit vector unit for matrix manipulations 166 MHz, 300 MIPS (DMIPS 1.1) Up to 664 Mbytes/s CPU bandwidth Direct mapped, on-chip, ICache (8 Kbytes) and DCache (16 Kbytes) Up to 100 MHz (1.6 Gbytes/s peak throughput) s PCI interface - 32-bit, 66/33 MHz, 3.3 V s Enhanced memory interface (EMI) q q q q q s High-performance 5-channel DMA engine, supporting 1D or 2D block.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com ST40RA 32-bit Embedded SuperH Device DATASHEET Integer & FP execution units JTAG JTAG Debug UDI SCIF SCIF Timer (TMU) Real-time clock Interrupt ctrl SuperHyway Clock ctrl Flash PLLs PCI I/F 66MHz ST40 Local Memory I/F Cbus Bridge/ SuperHyway I/F 5 channel DMA controller 2 channel control MPX Coprocessor EMI 32 data MMU I Cache MMU D Cache PIO interface Registers Mailbox 24 data 32 data PCI Peripherals 64 data SDRAM Peripherals Overview The ST40RA is the first member of the ST40 family. Based on the SH-4, SuperH CPU core from SuperH Inc, the ST40RA is designed to work as a standalone device, or as part of a two chip solution for application specific systems.