DESCRIPTION
OF THE ST92195 The Core has independent memory and register buses to add to the efficiency of the code. A set of on-chip peripherals form a complete system for TV set and VCR applications: Figure 1. ST92195 Block Diagram n 64K Bytes ROM 256 Bytes RAM MEMORY BUS NMI INT0 INT7 Oscin Oscout RESET 8K Bytes TDSRAM TRI 256 bytes Register File 8/16 bits CPU Interrupt Management ST9+ CORE RCCU 16-BIT TIMER/ WATCHDOG SPI TIMINGS CTRL UNIT STANDARD TIMER VOLTAGE SYNTHESIS 2/3 – Voltage Synthesis – VPS/WSS Slicer – Teletext Slicer – Teletext Display RAM – OSD Additional peripherals include a watchdog timer , a serial peripheral interface (SPI), a 16-bit timer and an A/D converter. I/O PORT 0 8 TELETEXT DATA SLICER SYNC. EXTRAC- TION VPS/WSS DATA SLICER I/O PORT 2 ADC/VS 6 ADC P0[7:0] CVBS1 WSCR WSCF CVBS2 TXCF AIN1 VS01 AIN2 VS02 AIN3 I/O PORT 3 SYNC CONTROL ON SCREEN DISPLAY I/O PORT 4 P.W.M Output P.W.M. D/A CONVERTER I/O PORT 5 (SPI) 4 PLL 8 RESET0 CSO CSO VSYNC HSYNC/ CSYNC PXFM/ R/G/B/FB PWM0 PWM7 EXTRG 2 SDO/SDI SCK VR02113A REGISTER BUS Notes: ST92195 Information furnished is believed to be accurate and reliable.
STMicroelectronics
