STMicroelectronics ST62T18C
The ST62T18C and ST62E18C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which are targeted at low to medium complexity applications. The ST62E18C is the erasable EPROM version of the ST62T18C device, which may be used to emulate the ST62T18C device, as well as the respective ST6218C ROM devices.GENERAL DESCRIPTION
1.1 INTRODUCTION All ST62xx devices are based on a building block approach: a common core is surrounded by a number of onchip peripherals. Figure 1. Block Diagram uct(s) TEST/VPP solete Prroodduct(s) NMI TEST 8-BIT A/D CONVERTER INTERRUPT PROGRAM Memory 7948 bytes DATA ROM USER SELECTABLE DATA RAM 192 Bytes ct(s) - Obbsolete P PC du - O STACK LEVEL 1 ro ) STACK LEVEL 2 P t(s STACK LEVEL 3 STACK LEVEL 4 te c STACK LEVEL 5 le du STACK LEVEL 6 8 BIT CORE so ro POWER OSCILLATOR RESET b P SUPPLY O leteVDDVSS OSCin OSCout RESET Obso (VPP on EPROM/OTP versions only) PORT A PORT B PORT D UART AUTORELOAD TIMER PA1 / 20 mA Sink PA2/ARTIMout / 20 mA Sink PA3/ARTIMin/ 20 mA Sink PA4..PA5/20 mA Sink PB4..PB6/Ain PD4/Ain/RXD1 PD5/Ain/TXD1 PD6,PD7/Ain TIMER TIMER DIGITAL WATCHDOG VR01823F 5/82 5 ST62T18C/E18C INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- Figure 2. ST62T18C/E18C Pin Configuration cal. The ROM based versions offer the same func- tionality sele...