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STA1275 - Automotive infotainment processors

Download the STA1275 datasheet PDF. This datasheet also covers the STA1295 variant, as both devices belong to the same automotive infotainment processors family and are provided as variant models within a single manufacturer datasheet.

General Description

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Key Features

  • AEC-Q100 qualified Grade 3 Core and infrastructure.
  • ARM® Single or Dual Core Cortex® A7 up to 650 MHz with NEON instructions and FPU.
  • Memory organization.
  • L1 Cache: 32 KB instruction, 32 KB data.
  • L2 Cache: 256 KB.
  • 768 KB embedded SRAM.
  • 16/32-bit DDR3L interface at 660 MHz.
  • Serial Quad IO NOR interface.
  • 16-bit Parallel NAND Controller.
  • 32-bit watchdog timer.
  • 16-channels DMA.
  • 8x 32-bit free.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (STA1295-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
STA1295, STA1275 Accordo5 - Automotive infotainment processors for display audio and cluster applications Datasheet - production data Features • AEC-Q100 qualified Grade 3 Core and infrastructure • ARM® Single or Dual Core Cortex® A7 up to 650 MHz with NEON instructions and FPU • Memory organization – L1 Cache: 32 KB instruction, 32 KB data – L2 Cache: 256 KB – 768 KB embedded SRAM – 16/32-bit DDR3L interface at 660 MHz – Serial Quad IO NOR interface – 16-bit Parallel NAND Controller • 32-bit watchdog timer • 16-channels DMA • 8x 32-bit free running timers/counters • 5x 16-bit Extended Function Timer (EFT) with input capture/output compare and PWM • Real Time Clock (RTC) with fraction readout • Temperature sensor Audio subsystem • Sound processing DSP (450 MIPS) • 6 stereo channels hard