STA2062A Description
DREQ0 DREQ1 DMA 1 DMA 0 M1 S M0 LCDC Interface ULPI Interface JTAG 16 KB I / 16K.
STA2062A Key Features
- High performance ARM926 MCU (up to 333 MHz) MCU memory organization
- Cache: 16 Kbyte instruction, 16 Kbyte data
- 8 Kbyte instruction TCM (tightly coupled memory)
- 8 Kbyte data TCM
- 32 Kbyte embedded ROM for boot
- Two banks of 64 Kbyte embedded SRAM
- 512 Byte embedded SRAM for back-up
- 4 Gbyte total linear address space
- Memory extension through: Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM support) Mobile DDR/
- 64-channel interrupt controller (VIC)