STMicroelectronics STB10NC50-1
The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics.DESCRIPTION
Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances.APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVEABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM (● ) P tot dv/dt( 1 ) Ts tg Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (RGS = 20 kΩ ) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction T emperature o o I2PAK D2PAK INTERNAL SCHEMATIC DIAGRAM Value 500 500 ± 30 10 6.3 40 135 1.08 3 -65 to 150 150 ( 1) ISD ≤ 10 A, di/dt ≤100 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Un it V V V A A A W W /o C V/ns o o C C (●) Pulse width limited by...