STM32H533CE Overview
Key Specifications
Key Features
- 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories
- 4-Kbyte data cache for external memories UFQFPN48 (7 x 7 mm) WLCSP39 (2.76 x 2.78 mm, pitch 0.4mm) Benchmarks
- 1.5 DMIPS/MHz (Drystone 2.1)
- 1023 CoreMark® (4.092 CoreMark®/MHz) Memories
- Up to 512 Kbytes of embedded flash memory with ECC, two banks read-while-write
- Up to 48-Kbyte per bank with high-cycling capability (100 K cycles) for data flash
- 2-Kbyte OTP (one-time programmable)
- 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)
- 2 Kbytes of backup SRAM available in the lowest power modes
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories
