STM32H7S3Z8 Datasheet | STMicroelectronics

Features Includes ST state-of-the-art patented technology Core - 32-bit Arm® Cortex®-M7 CPU with MPU and DP-FPU, L1 cache: 32+32-Kbyte instruction and data cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 600 MHz, 1284 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories - 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration. - SRAM: total 620 Kbytes (548 Kbytes with optional ECC activated) organized as follows: - 64+64 Kbytes minimum of instruction and data TCM RAM for critical real time instructions - 384 Kbytes AXI SRAM (128 Kbytes with optional remap to TCM RAM fully activated - 4 Kbytes of backup SRAM (available in the lowest-power modes) - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, FRAM, SDR/LPSDR SDRAM, NOR/NAND memories - up to 2x Octo-SPI memory interfaces or 1 octo SPI + 1 hexa-SPI with Xi P, with support for serial PSRAM/NAND/NOR, Hyper RAM™/ Hyper Flash™ frame formats running at up to 200 MHz - 2x SD/SDIO/MMC interfaces 2x DMA controllers to offload the CPU - 2 × dual-port DMAs with FIFO and linked listed support LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) UFBGA UFBGA LQFP176 (24 x 24 mm) UFBGA UFBGA144 (10 x 10 mm) UFBGA169 (7 x 7 mm) UFBGA176+25 (10 x 10 mm) TFBGA TFBGA VFQFPN WLCSP101 (die) TFBGA100 (8x8 mm) TFBGA225 (13 x 13 mm) VFQFPN68 (10 x 10 mm) Security and cryptography - PSA level 2 and SESIP level 3 certified (under certification) - Flexible life cycle scheme with debug authentication based on certificate or password (debug reopening/regression support) - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - Secure firmware installation / update (SFI/SFU) thanks to embedded root secure services (RSS) - Secure data storage with hardware unique key (HUK) - 2 AES coprocessors including one with DPA resistance - Public key accelerator, DPA resistant - On-the-fly...