STM32MP135F Datasheet | STMicroelectronics

STM32MP135C STM32MP135F Arm® Cortex®-A7 up to 1 GHz, LCD-TFT, camera interface, 2×ETH, 2×CAN FD, 2×ADC, 24 timers, audio, crypto and adv. security - production data Features Includes ST state-of-the-art patented technology Core - 32-bit Arm® Cortex®-A7 - L1 32-Kbyte I / 32-Kbyte D - 128-Kbyte unified level 2 cache - Arm® NEON™ and Arm® Trust Zone® Memories - External DDR memory up to 1 Gbyte - up to LPDDR2/LPDDR3-1066 16-bit - up to DDR3/DDR3L-1066 16-bit - 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain - Dual Quad-SPI memory interface - Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC Security/safety - Secure boot, Trust Zone® peripherals, 12 x tamper pins including 5 x active tampers - Temperature, voltage, frequency and 32 k Hz monitoring Reset and power management - 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) - POR, PDR, PVD and BOR - On-chip LDOs (USB 1.8 V, 1.1 V) - Backup regulator (~0.9 V) - Internal temperature sensors - Low-power modes: Sleep, Stop, LPLV-Stop, LPLV-Stop2 and...