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STM32MP257F - MPU

This page provides the datasheet information for the STM32MP257F, a member of the STM32MP251C MPU family.

Datasheet Summary

Features

  • Includes ST state-of-the-art patented technology. Cores.
  • Up to 64-bit dual-core Arm® Cortex®-A35.
  • Up to 1.5 GHz.
  • 32-Kbyte I + 32-Kbyte D level 1 cache for each core.
  • 512-Kbyte unified level 2 cache.
  • Arm® NEON™ and Arm® TrustZone®.
  • 32-bit Arm® Cortex®-M33 with FPU/MPU.
  • Up to 400 MHz.
  • L1 16-Kbyte I / 16-Kbyte D.
  • Arm® TrustZone®.
  • 32-bit Arm® Cortex®-M0+ in SmartRun domain.
  • Up to 200 MHz (up to 16 MHz.

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Full PDF Text Transcription

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STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F Datasheet Arm® based dual Cortex®-A35 1.5 GHz + Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto TFBGA361 (16 × 16 mm) pitch 0.8 mm VFBGA361 (10 × 10 mm) pitch 0.5 mm VFBGA424 (14 × 14 mm) pitch 0.5 mm TFBGA436 (18 × 18 mm) pitch 0.8 mm Product summary STM32MP25xC/F STM32MP251C, STM32MP251F, STM32MP253C, STM32MP253F, STM32MP255C, STM32MP255F, STM32MP257C, STM32MP257F Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.
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