STM8AF6166 Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . .
STM8AF6166 Key Features
- Max fCPU: 16 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark
- Program memory: 16 to 32 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
- Data memory: 0.5 to 1 Kbyte true data EEPROM; endurance 300 kcycles
- RAM: 1 to 2 Kbytes
- LINUART LIN 2.1 pliant, master/slave modes with automatic resynchronization
- SPI interface up to 8 Mbit/s or fCPU/2
- I2C interface up to 400 Kbit/s
- Analog-to-digital converter (ADC)