STM8AF6223A Description
12 4.1 Central processing unit (CPU) . 12 4.1.1 Architecture and registers . 12 4.1.3 Instruction set.
STM8AF6223A Key Features
- AEC-Q100 qualified
- Max fCPU: 16 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Extended instruction set
- Memories
- Program memory: 4 to 8 Kbyte Flash program; data retention 20 years at 55 °C after 1 kcycle
- Data memory: 640 byte true data EEPROM; endurance 300 kcycle
- RAM: 1 Kbyte
- Clock management
- Low-power crystal resonator oscillator with external clock input