STM8AF6388 Overview
14 5.1 STM8A central processing unit (CPU) . 14 5.1.1 Architecture and registers.
STM8AF6388 Key Features
- AEC-Q10x qualified
- Max fCPU: 24 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark
- Memories
- Program memory: 32 to 128 Kbyte Flash program; data retention 20 years at 55 °C
- Data memory: up to 2 Kbyte true data EEPROM; endurance 300 kcycle
- RAM: 6 Kbyte
- Clock management
- Low-power crystal resonator oscillator with external clock input