STMicroelectronics STM8L101G2
The STM8L101x1 STM8L101x2 STM8L101x3 low-power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming. The 8-Kbyte devices embed data EEPROM.FEATURES
● Main microcontroller features – Supply voltage range 1.65 V to 3.6 V – Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz) – STM8 Core with up to 16 CISC MIPS throughput – Temp. range: -40 to 85 °C and 125 °C● Memories – Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM
● Clock management – Internal 16 MHz RC with fast wakeup time (typ. 4 µs) – Internal low consumption 38 kHz RC driving both the IWDG and the AWU
● Reset and supply management – Ultra-low power POR/PDR – Three low-power modes: Wait, Active-halt, Halt
● Interrupt management – Nested interrupt controller with software priority control – Up to 29 external interrupt sources
● I/Os – Up to 30 I/Os, all mappable on external interrupt vectors – I/Os with programmable input pull-ups, high sink/sourc...