STM8S001J3
Overview
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set Memories
- Program memory: 8-Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
- RAM: 1 Kbyte
- Data memory: 128-byte true data EEPROM; endurance up to 100 k write/erase cycles Clock, reset and supply management
- 2.95 V to 5.5 V operating voltage
- Flexible clock control, 3 master clock sources - External clock input - Internal, user-trimmable 16 MHz RC - Internal low-power 128 kHz RC
- Clock security system with clock monitor
- Power management - Low-power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually - Permanently active, low-consumption power-on and power-down reset Interrupt management
- Nested interrupt controller with 32 interrupts
