STM8S001J3 Overview
10 4 Functional overview . 11 4.1 Central processing unit STM8 . .11 4.2 Single wire interface module (SWIM) and debug module (DM).
STM8S001J3 Key Features
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set
- Program memory: 8-Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
- RAM: 1 Kbyte
- Data memory: 128-byte true data EEPROM
- 2.95 V to 5.5 V operating voltage
- Flexible clock control, 3 master clock sources
- External clock input
- Internal, user-trimmable 16 MHz RC
- Internal low-power 128 kHz RC