STMicroelectronics STP11NB40FP
The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics.DESCRIPTION
Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances.APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVEABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID I DM (● ) P tot dv/dt( 1 ) V ISO Ts tg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 oC Drain Current (pulsed) T otal Dissipation at Tc = 25 o C Derating Factor Peak Diode Recovery voltage slope Insulation W ithstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value ST P11NB40 STP11NB40F P 400 400 ± 30 10.7 6.7 42.8 125 1.0 4.5 -65 to 150 150 ( 1) ISD ≤ 10.7A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS...