STPC Datasheet | STMicroelectronics

STPC® CONSUMER-II X86 Core PC patible Information Appliance System-on-Chip s s .. POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER VGA & SVGA CRT CONTROLLER 135 MHz RAMDAC 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT TV OUTPUT - THREE-LINE FLICKER FILTER - ITU-R 601/656 SCAN CONVERTER - NTSC / PAL POSITE, RGB, S-VIDEO PCI MASTER / SLAVE / ARBITER ISA MASTER / SLAVE OPTIONAL 16-BIT LOCAL BUS INTERFACE EIDE CONTROLLER I²C INTERFACE IPC - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS POWER MANAGEMENT UNIT JTAG IEEE1149.1 Video Pipeline SVGA CRTC C Key K Key LUT ST PC Co ns um s s s s s er PBGA388 s Figure 0-1. Logic Diagram s s s s s s Host I/F x86 Core PCI m/s PMU IPC ISA m/s PCI m/s IDE I/F PCI Bus ISA Bus s s LB CTR Local Bus DESCRIPTION The STPC Consumer-II integrates a standard 5th generation x86 core, a Synchronous DRAM controller, a graphics subsystem, a video pipeline, and support logic including PCI, ISA, and IDE controllers to provide a single consumer orientated PC patible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing memory between the CPU, the graphics and the video. The STPC Consumer-II is packaged in a 388 Plastic Ball Grid Array (PBGA). Monitor Cursor Encoder GE VIP SDRAM CTRL JTAG Release...