STQ1HNC60 Datasheet PDF

DESCRIPTION

Using the latest high voltage MESH OVERLAY™II process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS

s SWITCH MODE LOW POWER SUPPIES (SMPS) s CFL

ABSOLUTE MAXIMUM RATINGS

Symbol VDS VDGR VGS ID ID IDM (q) PTOT dv/dt(1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 600 600 ± 30 0.4 0.25 1.6 3.5 0.028 3.5 –65 to 150 150 (1)ISD ≤ 0.4 A, di/dt ≤100A/µs, V DD ≤ V(BR)DSS, Tj ≤ T JMAX.