STR911FAW42 Overview
12 3.1 3.2 3.3 3.4 System-in-a-Package (SiP).
STR911FAW42 Key Features
- ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)
- STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache
- Up to 96 MIPS directly from Flash memory
- Single-cycle DSP instructions supported
- Binary patible with ARM7 code Dual burst Flash memories, 32-bits wide
- 256 KB/512 KB/1 MB/2 MB Main Flash
- 32 KB/128 KB Secondary Flash
- Sequential Burst operation up to 96 MHz
- 100 K min erase cycles, 20 yr min retention SRAM, 32-bits wide
- 96K bytes, optional battery backup 9 programmable DMA channels Clock, reset, and supply management