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STV2050A - AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR

General Description

AND PINOUT DIAGRAM 8 2 STRUCTURE OF THE PROGRAMMING SYSTEM

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Key Features

  • 14 3.1.1 ADS0: IC Address and PLL Mode.
  • . . . 3.1.2 SCLS Bus Clock.
  • . 3.1.3 SDAI Bus Data Input.
  • . . . 3.1.4 SDAO Bus Data Output.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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STV2050A AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR s s s s s s s s s s s s s Multiscan 1H, 2H, HDTV and SVGA applications 6 Convergence channels 14-bit embedded DACs 1 Focus channel Second order interpolation in vertical direction Digital filtering in horizontal direction On-chip PLL On-chip video pattern generator Automatic compensation of temperature drift and aging of external components Pattern and synchronisation signals for optional optical sensor support Adjustable horizontal and vertical size Up to 7 different data sets Self-controlled power-on sequence Package: PQFP80 Power Supply: 3.3 V Tape and Reel: STV2050ATR Figure 1.