DESCRIPTION
Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842T and UC3843T can operate to duty cycles approaching 100%. A range of zero to < 50 % is obtained by the UC3844T and UC3845T by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGRAM (toggle flip flop used only in UC3844T and UC3845T) Vi 7 34V GROUND 5 UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC RT/CT 4 OSC ERROR AMP. 2R R 1V T 8 VREF 5V 50mA 2.50V 6 OUTPUT VFB COMP CURRENT SENSE 2 1 3 + - S R CURRENT SENS...
STMicroelectronics
