GENERAL DESCRIPTION
W.A.R.P. is a VLSI Fuzzy Logic controller whose architecture arises from the need of realizing an integrated structure with high inferencing performances and flexibility. To get those results a modular architecture based on a set of parallel memory blocks has been implemented. In order to obtainhigh performances W.A.R.P. uses different data representations during the various phases of the computational cycle, so that it is always operating on the optimal data representation. A vectorial characterization has been adopted for the Antecedent Membership Functions. W.A.R.P. exploits a SGS-THOMSON patented strategy to store the AntecedentMembership Table 1. W.A.R.P. Configuration Settings Number of Inputs Standard Rule Format Rules Number Antecedent’s MFs Number Consequent’s MFs Number Input Data Resolution Output Data Resolution Configurable [1..8] 4 Antecedents, 1 Consequent [or subsets] Max 256 Rules in the 4 Antecedent, 1 Consequent format Configurable [up to 16 for an input variable] Max 256 for all outputs variables 8 bit 8 bit CPGA 100 PLCC84 Figure 1.
STMicroelectronics
