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WS57C71C Datasheet PDF

STMicroelectronics WS57C71C

The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device.
Part No. WS57C71C
Datasheet WS57C71C Download
Manufacturer
STMicroelectronics
Description HIGH SPEED 32K x 8 CMOS PROM/RPROM
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WS57C71C datasheet page 1 preview

FEATURES

● Immune to Latch-UP — Up to 200 mA
● Low Power Consumption
● Fast Programming
● ESD Protection Exceeds 2000V
● Available in 300 Mil DIP and PLDCC

GENERAL DESCRIPTION

This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The DIP version is packaged in a 300 mil wide DIP package saving board space for the user. BLOCK DIAGRAM PIN CONFIGURATION TOP VIEW Chip Carrier CERDIP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A10 A11 A12 A13 A14 CS3 CS2 CS1/VPP O7 O6 O5 O4 O3 9 A6 - A14 ROW ADDRESSES ROW DECODER 262,144 BITS 9 A0 - A5 COLUMN ADDRESSES COLUMN DECODER SENSE AMPLIFIERS A6 A5 A4 A3 A2 A1 A0 NC O0 CS1/ VPP CS2 CS3 8 32 31 30 1 5 29...
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