STP3010 Overview
The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures. This chip provides an integral SBus interface, VRAM (video random-access memory) controller, a high-performance math engine, plus a high-performance rendering (or drawing) engine. A plete graphics accelerator can be built utilizing this chip, a clock device, VRAM, and a RAMDAC.
STP3010 Key Features
- 100 percent patibility with previous GX implementations
- plete graphics accelerator in a single chip-just a