DESCRIPTION
All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. ), Count Enable Three control inputs — Parallel Enable (PE Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below . The Count , and PE inputs are HIGH. Mode is enabled when the CEP , CET , the counters will synchronously load the When the PE is LOW data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND...
SYC
