SDP65N03L Datasheet PDF

S DP /B 65N03L S amHop Microelectronics C orp. May,2004 ver1.1 N-Channel Logic Level E nhancement Mode Field E ffect Transistor 4 P R ODUC T S UMMAR Y V DS S 30V F E AT UR E S ( m W ) Max ID 62A R DS (on) S uper high dense cell design for extremely low R DS (ON). High power and current handling capability. TO-220 & TO-263 package. 9 @ V G S = 10V 15 @ V G S = 4.5V D D G D S G S G S DP S E R IE S TO-220 S DB S E R IE S TO-263(DD-P AK) S ABS OLUTE MAXIMUM R ATINGS (TC =25 C unless otherwise noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous -P ulsed a S ymbol V DS V GS @ TJ=125 C ID IDM IS PD T J , T S TG Limit 30 20 62 186 65 75 -65 to 175 Unit V V A A A W C Drain-S ource Diode Forward C urrent Maximum P ower Dissipation @ Tc=25 C Operating and S torage Temperature R ange THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient 1 R JC R JA 2 C /W C /W 62.5 S DP /B 65N03L E LE CTR ICAL CHAR ACTE...