STD3525NLS Datasheet PDF

S T U/D3525NLS S amHop Microelectronics C orp. Aug 06 , 2005 N-C hannel Logic Level E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y V DS S 25V F E AT UR E S (mW) ID 35A R DS (ON) Max S uper high dense cell design for low R DS (ON ). 16 @ V G S = 10V 25 @ V G S = 4.5V R ugged and reliable. TO-252 and TO-251 P ackage. D D G S G D S G S TU S E R IE S TO-252AA(D-P AK) S TD S E R IE S TO-251(l-P AK) S ABS OLUTE MAXIMUM R ATINGS (T A=25 C unless otherwise noted) P arameter Drain-S ource Voltage R ating Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a -P ulsed @ T C =25 C S ymbol Vspike C V DS V GS ID IDM IS PD T J , T S TG Limit 30 25 20 35 75 20 50 -55 to 175 Unit V V V A A A W C Drain-S ource Diode Forward C urrent Maximum P ower Dissipation @ Tc=25 C Operating and S torage Temperature R ange THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient 1 R JC R JA 3 50 C /W C /W S T U/D3525NLS E LE C...