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KM416S1020C
CMOS SDRAM
1M x 16 SDRAM
512K x 16bit x 2 Banks Synchronous DRAM LVTTL
Revision 0.6 September 1998
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Rev. 0.6 (Sep. 1998)
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KM416S1020C
Revision History
Revision 0.6 (September 10, 1998)
CMOS SDRAM
• Removed KM416S1020C-H/L product (-H: 100MHz @ CL=2, -L: 100MHz @ CL3 ) • Changed the clock cycle time of KM416S1020C-8 @ CL2 from 12ns to 10ns, accordingly, the AC and DC parameters of KM416S1020C-8 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V • Changed ICC1 of KM416S1020C-7 @ CL2 from 115mA to 120mA in DC CHARACTERISTICS.