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KM416S1020C - 1M x 16 SDRAM

General Description

The KM416S1020C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM.

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Other Datasheets by Samsung Semiconductor

Part Number Description
KM416S1021C 512K x 16-Bit x 2-Bank SDRAM
KM416S4030C 1M x 16Bit x 4 Banks Synchronous DRAM
KM416S8030 2M x 16Bit x 4 Banks Synchronous DRAM
KM416S8030B 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
KM416S8030BN 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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KM416S1020C CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 0.6 September 1998 Samsung Electronics reserves the right to change products or specification without notice. w w w . t a d h s a t e e . u 4 m o c -1- Rev. 0.6 (Sep. 1998) www.DataSheet4U.com KM416S1020C Revision History Revision 0.6 (September 10, 1998) CMOS SDRAM • Removed KM416S1020C-H/L product (-H: 100MHz @ CL=2, -L: 100MHz @ CL3 ) • Changed the clock cycle time of KM416S1020C-8 @ CL2 from 12ns to 10ns, accordingly, the AC and DC parameters of KM416S1020C-8 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V • Changed ICC1 of KM416S1020C-7 @ CL2 from 115mA to 120mA in DC CHARACTERISTICS.