K4C89323AF Overview
K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as 2,097,152-words x 4 banks x36 bits.
K4C89323AF Key Features
- R e f r e s h C u r r e n t ( m a x )
- Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS
- Differential Clock (CLK and C L K ) inputs
- C S, FN and all address input signals are sampled on the positive edge of CLK
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK
- Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum