K4H511638G
Key Features
- VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
- Four banks operation
- Differential clock inputs(CK and CK)
- DLL aligns DQ and DQS transition with CK transition
- MRS cycle with address key programs
- Burst type (sequential & interleave)
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
- Data I/O transactions on both edges of data strobe
