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K4S281632B-N - 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP

General Description

The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle).

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S281632B-TC10 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC1H 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC1L 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC75 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC80 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

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shrink-TSOP K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.