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K4S281632C-TC1H - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Description

The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S281632C-TC1L 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TC75 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TI 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TI1H 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TI1L 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K4S281632C CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Mar. 2000 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Mar. 2000 K4S281632C Revision History Revision 0.0 (March 21, 2000) • Changed tOH of K4S280432C-TC75/TL75 from 2.7ns to 3.0ns. • Deleted -10 and -80 speed specification. CMOS SDRAM Rev. 0.0 Mar. 2000 K4S281632C 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
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