Datasheet4U Logo Datasheet4U.com

K4S281632C-TP1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Description

The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
K4S281632K 128Mb K-die SDRAM Samsung
K4S280832B 128M-bit SDRAM Samsung Electronics
K4S1G0632D SDRAM stacked 1Gb D-die Samsung Electronics
K4S1G0732D SDRAM stacked 1Gb D-die Samsung Electronics
K4S510432D 512Mb D-die SDRAM Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
K4S281632C-TP1H 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TP 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TP75 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TC1H 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632C-TC1L 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S281632C-TI(P) CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) Revision History Revision 0.0 (November 18, 2000) • First generation. CMOS SDRAM Revision 0.1 (June 20, 2001) • Final Specification. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
Published: |