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K4S281632F-Txx - 128Mb F-die SDRAM

Description

The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM (x4,x8) & L(U)DQM (x16) for masking.
  • Auto & self refresh.
  • 64ms.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM 128Mb F-die SDRAM Specification m o .c U 4 t e e h S a t a .D w Revision 1.1 w February 2004 w * Samsung Electronics reserves the right to change products or specification without notice. m o .c U 4 t e e h S a at February 2004 Rev. 1.1 .D w w w SDRAM 128Mb F-die (x4, x8, x16) Revision History Revision 0.0 (Agust, 2003) - First release. Revision 0.1 (November, 2003) - completed DC characteristics. Revision 0.2 (November, 2003) - Preliminary spec release. Revision 1.0 (January, 2004) - Revision 1.0 spec release. - Modified ICC4 current from 110mA -> 140mA at x16 - Modified tSH from 0.8ns -> 1.0ns at 166MHz. Revision 1.1 (February, 2004) - Corrected typo. CMOS SDRAM Rev. 1.
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