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K4S281633D-N75 Datasheet 8Mx16 SDRAM 54CSP

Manufacturer: Samsung Semiconductor

Overview: Preliminary K4S281633D-RL(N) CMOS SDRAM 8Mx16 SDRAM 54CSP (V DD/V DDQ 3.0V/3.0V & 3.3V/3.3V) Revision 0.6 November 2001 Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) Revision History Revision 0.0 (February 21. 2001, Target) CMOS SDRAM • First generation of 128Mb Low Power SDRAM without special function (V DD 3.0V, V DDQ 3.0V) Revision 0.1 (June 4. 2001, Target) • Addition of DC Current value. Revision 0.2 (June 20. 2001, Target) • Changed device name from low power sdram to mobile dram. Revision 0.3 (August 1. 2001, Target) • Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. • Change of tOH from 3ns to 3.5ns. • Change V IH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ. Revision 0.4 (October 6. 2001, Preliminary) • Changed DC current. • Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part. • Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part. • Changed of tOH from 3ns to 2.5ns. • Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part. • Integration of VDDQ 1.8V device and 2.5V device. • Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ. • Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V. • Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA. • Erased -15 bin and added -1H bin. Revision 0.5 (October 12. 2001, Preliminary) • Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V. • Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V. Revision 0.6 (November 7. 2001, Preliminary) • Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V. Rev. 0.6 Nov.

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Key Features

  • 3.0V & 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto refresh.
  • 64ms refresh period (4K cycle.

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