K4S511533F-YPC Datasheet PDF (8M x 16Bit x 4 Banks Mobile SDRAM) | Download Samsung semiconductor K4S511533F-YPC

K4S511533F-YPC - 8M x 16Bit x 4 Banks Mobile SDRAM

This page provides the datasheet information for the K4S511533F-YPC, a member of the K4S511533F-YC 8M x 16Bit x 4 Banks Mobile SDRAM family.

Description

The K4S511533F is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

3.0V & 3.3V power supply.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
Special Function Support. -. PASR.

Datasheet Details

Part number	K4S511533F-YPC
Manufacturer	Samsung semiconductor
File Size	137.01 KB
Description	8M x 16Bit x 4 Banks Mobile SDRAM
Datasheet	K4S511533F-YPC Datasheet
Additional preview pages of the K4S511533F-YPC datasheet.

📁 Similar Datasheet

K4S511632D - 512Mb D-die SDRAM (Samsung)

K4S510432D - 512Mb D-die SDRAM (Samsung)

K4S510832D - 512Mb D-die SDRAM (Samsung)

K4S560432E-UC75 - SDRAM 256Mb E-die (Samsung)

K4S560832E-UC75 - SDRAM 256Mb E-die (Samsung)

K4S561632C - 256Mbit SDRAM (Samsung)

K4S561632E-UC60 - SDRAM 256Mb E-die (Samsung)

K4S561632E-UC75 - SDRAM 256Mb E-die (Samsung)

K4S561632H - 256Mb H-Die SDRAM (Samsung Electronics)

K4S1G0632D - SDRAM stacked 1Gb D-die (Samsung Electronics)

Full PDF Text Transcription

Click to expand full text

K4S511533F - Y(P)C/L/F 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (8K cycle). Commercial Temperature Operation (-25°C ~ 70°C). 2 /CS Support. 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).

Published: Apr 12, 2010 |