K4S511632M-TC Datasheet | Samsung Semiconductor

FEATURES - JEDEC standard 3.3V power supply - LVTTL patible with multiplexed address - Four banks operation - MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) - All inputs are sampled at the positive going edge of the system clock. - Burst read single-bit write operation - DQM for masking - Auto & self refresh - 64ms refresh period (8K cycle) Part No. K4S511632M-TC/TL75 K4S511632M-TC/TL1H K4S511632M-TC/TL1L CMOS SDRAM GENERAL DESCRIPTION The K4S511632M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Max Freq. 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL Interface Package 54pin TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LDQM Bank Select 8M x 16 8M x 16 8M x 16 8M x 16 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing...