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K4S640432D - 64Mbit SDRAM 4M x 4Bit x 4 Banks Synchronous DRAM LVTTL

General Description

The K4S640432D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle).

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Other Datasheets by Samsung Semiconductor

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K4S640432H-UC75 64Mb H-die SDRAM Specification 54 TSOP-II

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K4S640432D CMOS SDRAM 64Mbit SDRAM 4M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Jun. 1999 K4S640432D 4M x 4Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -.