K4S640432H-TC Overview
. Rev. 1.4 November 2003 SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM 4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous.
K4S640432H-TC Key Features
- JEDEC standard 3.3V power supply
- LVTTL patible with multiplexed address
- Four banks operation
- MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Seque
- All inputs are sampled at the positive going edge of the system clock
- Burst read single-bit write operation
- DQM (x4,x8) & L(U)DQM (x16) for masking
- Auto & self refresh
- 64ms refresh period (4K cycle)