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K4S643232E Datasheet 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl(3.3v)

Manufacturer: Samsung Semiconductor

Overview: K4S643232E CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.3 October 2001 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.3 (Oct. 2001) K4S643232E Revision History Revision 1.3 (October 24, 2000) • Removed CAS Latency 1 from the spec. CMOS SDRAM Revision 1.2 (August 7, 2000) - Target • Added CAS Latency 1 Revision 1.1 (March 14, 2001) • Added K4S643232E-55 Revision 1.0 (October 20, 2000) • Removed Note 5 in page 9. tRDL is set to 2CLK in any case regardless of using AP or frequency Revision 0.4 (August 24, 2000) • Updated DC spec Revision 0.3 (August 1, 2000) • Changed the wording of tRDL related note for User’ s clear understanding Revision 0.2 (July 18, 2000) - Preliminary • Removed K4S643232E-40/55/7C • Changed tSH of K4S643232E-45 from 0.7ns to 1.0ns Revision 0.0 (March 14, 2000) - Target Spec. • Initial draft -2- Rev. 1.3 (Oct.

General Description

The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock.

I/O transactions are possible on every clock cycle.

Key Features

  • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle CMOS SDRAM.

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More Datasheets from Samsung Semiconductor

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