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K7A161831B - 18MB B-DIE SYNC SRAM SPECIFICATION 100TQFP WITH PB / PB-FREE

This page provides the datasheet information for the K7A161831B, a member of the K7A163631B 18MB B-DIE SYNC SRAM SPECIFICATION 100TQFP WITH PB / PB-FREE family.

Datasheet Summary

Description

The K7A163631B and K7A161831B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 2.5 or 3.3V +/- 5% Power Supply.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • LBO Pin allows a choice of either a interleaved burst.

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Datasheet preview – K7A161831B

Datasheet Details

Part number K7A161831B
Manufacturer Samsung semiconductor
File Size 405.57 KB
Description 18MB B-DIE SYNC SRAM SPECIFICATION 100TQFP WITH PB / PB-FREE
Datasheet download datasheet K7A161831B Datasheet
Additional preview pages of the K7A161831B datasheet.

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Full PDF Text Transcription

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K7A163631B K7A161831B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
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