KM681002C Datasheet | Samsung Semiconductor

PRELIMINARY KM681002C/CL, KM681002CI/CLI Document Title 128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at mercial and Industrial Temperature Ranges. CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to Final Data Sheet. 1.1. Delete Preliminary. 2.2. Added Data Retention Characteristics. Add 10ns part. Draft Data Aug. 5. 1998 Mar. 3. 1999 Remark Preliminary Final .. Rev. 2.0 Mar. 3. 2000 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 2.0 March 2000 PRELIMINARY KM681002C/CL, KM681002CI/CLI Features - Fast Access Time 10,12,15,20ns(Max.) - Low Power Dissipation Standby (TTL) : 30m A(Max.) (CMOS) : 5m A(Max.) 0.5m A(Max.) L-ver. only Operating KM681002C/CL-10 : 80m A(Max.) KM681002C/CL-12 : 75m A(Max.) KM681002C/CL-15 : 73m A(Max.) KM681002C/CL-20 : 70m A(Max.) - Single 5.0V±10% Power Supply - TTL patible Inputs and Outputs .. - I/O patible with 3.3V Device - Fully Static Operation - No Clock or Refresh required - Three State Outputs - 2V Minimum Data Retention; L-ver. only - Center Power/Ground Pin Configuration - Standard Pin Configuration KM681002C/CLJ : 32-SOJ-400 KM681002C/CLT : 32-TSOP2-400CF CMOS SRAM GENERAL DESCRIPTION The KM681002C is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002C uses 8 mon input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well...