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KS57C0301 Datasheet (ks57c0301 / Ks57c0302) Single-chip CMOS Microcontroller

Manufacturer: Samsung Semiconductor

Overview: KS57C0301/0302 MICROCONTOLLER PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVER VIEW The KS57C0301/0302 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core. With parator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit timer/counter, the KS57C0301/0302 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. Up to 15 pins of the 20-pin DIP or 20-pin SOP package can be dedicated to I/O. Pull-up resistors are assignable to all of the pins by software. Four vectored interrupts provide fast response to internal and external events. In addition, the KS57C0301/0302's advanced CMOS technology provides for very low power consumption and a wide operating voltage range. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a plete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its easy to use window-oriented program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard object files that also contain program control data for SMDS patibility.

Key Features

  • Memory.
  • 1024 × 8-bit program memory (KS57C0301) (ROM).
  • 2048 × 8-bit program memory (KS57C0302) (ROM).
  • 128 × 4-bit data memory (KS57C0301) (RAM).
  • 256 × 4-bit data memory (KS57C0302) (RAM).
  • 8-bit receive-only mode.
  • LSB-first or MSB-first transmission selectable.
  • Internal or external clock source Interrupts.
  • One external interrupt vector.
  • Three internal interrupt vectors.
  • Two quasi-interrupts Memory-Mapped I/.

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