KT8555J Datasheet | Samsung Semiconductor

FEATURES l l l l l l l l Single, 5V operation Low power consumption: 5m W Controls four 1 CHIP CODEC Independent transmit and receive frame syncs enables channel unidirectional mode Up to 64 time slots per frame patible with KT8554/7 CODECs TTL and CMOS patible ORDERING INFORMATION Device KT8555J Package 20-CERDIP Operating Temperature - 20°C ~ + 125°C PIN CONFIGURATION FSX1 FSR1 FSX0 FSR0 TSX DC CLKC CS MODE 1 2 3 4 5 6 7 8 9 20 VCC 19 FSR2 18 FSX2 17 FSR3 16 FSX3 15 CH0 14 CH1 13 RSYC/CH2 12 XSYC 11 BCLK KT8555 GND 10 Fig. 1 KT8555 PIN DESCRIPTION Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10 11 12 Symbol FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 TSX DC CLKC CS MODE GND BCLK XSYC TIME SLOT ASSIGNMENT CIRCUIT Description A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. This pin pulls low during any active transmit time slot. (N-channel open drain) The input for an 8 bit serial control word. X is the first bit clocked in. The clock input for the control interface. The active-low chip select for the control interface. Mode 1 = Open or VCC Mode 2 = Gnd Ground The bit clock input (2.048 MHz) The transmit TSO sync pulse input. Must be synchronous with BCLK. The transmit time slot 0 sync pulse input. Must be synchronous with BCLK. RSYC /CH2 In mode 1 this input is the receive time slot 0 sync pulse, RSYC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. 14 15 20 CH1 CH0 VCC The input for the NSB (next significant bit) of the channel select word. The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. Power supply pin. 5V ±5% ABSOLUTE MAXIMUM RATINGS Characteristic Positive Supply...