S3C72B5 Datasheet | Samsung Semiconductor

OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-1280-dot LCD direct drive capability, segment expandable circuit, 8-bit and 16-bit timer/counter, and serial I/O, the S3C72B5/C72B7/C72B9 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 51 pins of the 128-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide fast response to internal and external events. In addition, the S3C72B5/C72B7/C72B9's advanced CMOS technology provides for low power consumption and a wide operating voltage range. The S3C72B5/C72B7/C72B9 microcontroller is also available in OTP (One Time Programmable) version, S3P72B9. S3P72B9 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P72B9 is parable to S3C72B5/C72B7/C72B9, both in function and in pin configuration except ROM size. 1-1 PRODUCT OVERVIEW S3C72B5/C72B7/C72B9/P72B9 FEATURES SUMMARY Memory - 3,584 × 4-bit RAM (Excluding LCD Display RAM) 16,384/24,576/32,768 × 8-bit ROM 16-Bit Timer/Counter - - - - 51 I/O Pins - - I/O: 47 pins (32 pins are configurable as SEG pins) Input only: 4 pins - - Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider Configurable as two 8-bit Timers Serial I/O interface clock generator Bit Sequential Carrier - Supports 16-bit serial data transfer in arbitrary format - Memory-Mapped I/O Structure - Data memory bank 15 Power-Down Modes - - - Idle mode (only CPU clock stops) Stop mode (main system clock stops) Subsystem clock stop mode LCD Controller/Driver - - - - - 80 SEG × 16 , 88 SEG × 8 Terminals Internal resistor circuit for LCD bias 16 Level LCD contrast control (software) Segment expandable circuit All dot can be switched on/off Watch...